BL54LM20A Series - Bluetooth LE + 802.15.4 + NFC

Yes, Bluetooth Channel Sounding requires specific hardware features and hence not every BLE radio can do Channel Sounding. Below is a breakdown of why specific hardware is required:

1. New Hardware Capabilities

• Unique Radio Requirements: The Channel Sounding (CS) feature mandates specialized hardware capable of performing Phase-Based Ranging (PBR) and Round-Trip Time (RTT) measurements.
• Specific SoCs: Currently, this functionality is supported by next-generation SoCs like the Nordic nRF54L15/L10 and nRF54H20 series. Older BLE chips (e.g., nRF52 series) do not have the necessary radio circuitry to generate these specific tones or handle the precise timing required.
• Antenna Requirements: For maximum accuracy, the hardware often requires dual-antenna support to perform angle-of-arrival calculations, which is not present in all BLE devices. 

2. Specialized Packet Formats and Tone Generation

• CS Sync Packets: These are not standard advertising or data packets. They are specialized packets with cryptographic protections (using a dedicated CS Deterministic Random Bit Generator) used for synchronizing timing between the Initiator and Reflector.
• CS Tone Packets: These are Amplitude Shift Keying (ASK) modulated tones used to measure phase rotation to determine distance. This requires specific analog radio hardware to generate and detect these tones rather than just typical GFSK modulation. 

3. Tight Timing Requirements

• Channel sounding requires extreme timing precision to calculate distance via RTT (Time of Flight). The CS step involves rapid, bi-directional exchanges of packets and tones, often with very fast frequency hopping (T_FCS). This cannot be supported by traditional BLE firmware/hardware. 

On the nRF54 family, peripheral instances that share the same ID and base address (e.g., SPIM00, SPIS00, TWIM00, UARTE00, all mapped to the same ID) cannot be used simultaneously. You must disable one peripheral before enabling another on that same ID, specifically clearing the peripheral's ENABLE register.

Here is a breakdown of simultaneous usage, restrictions, and shared resources based on the nRF54L15 architecture:

Peripherals That Cannot Be Used Simultaneously

• Shared Instance ID Peripherals: Peripherals with the same ID, such as SPI00, SPIM00, SPIS00, TWI00, TWIM00, TWIS00, and UARTE00 (collectively 00), are mutually exclusive. Only one can be active at a time.
• Pin-Colliding Peripherals: If two peripherals are assigned to the same GPIO pin through the PSEL register, they cannot operate simultaneously.
• QSPI/SPIM00 Limitations: While sQSPI (soft QSPI) and SPIM00 can often coexist, they cannot share the same pins, and on some configurations, the QSPI CSN pin is shared with the SPIM CSN, preventing simultaneous operation.
• Radio and High-Speed Peripherals: While high-speed UARTE (up to 4 Mbps) and SPIM (up to 32 MHz) can run simultaneously with other peripherals, extreme bus traffic may impact real-time performance.

Peripherals That Can Be Used Simultaneously

• Different Instances: You can run multiple instances of similar peripherals simultaneously if they have different IDs (e.g., UARTE20 and UARTE00 can run at the same time, as they are in different power domains).
• Dedicated Peripherals: Peripherals with unique IDs in the address map (e.g., QSPI and ADC, or Timers and PWM) can generally be used at the same time.
• VPR Core (FLPR) and Main CPU: The FLPR (Fast Lightweight Peripheral Processor) can handle specific peripherals (like I2C/SPI) in parallel with the main ARM Cortex-M33 processor.
• DPPI (Distributed Programmable Peripheral Interconnect): You can connect events and tasks between multiple independent peripherals without CPU intervention.

Key Limitations and Rules

• Power Domains: Peripherals with numeric IDs starting with 2 (e.g., UARTE20) are in the Peripheral domain (16 MHz), while those with 0 (e.g., UARTE00) are in the MCU domain (128 MHz). Mixing them generally allows for concurrent operation.
• P2 Port Conflict: The Peripheral domain uses dedicated GPIO Port 2 (P2). If multiple peripherals are assigned to the same P2 pins, they will conflict.
• Switching Rule: To switch between two peripherals sharing an ID:
  • Disable the previously used peripheral.
  • Disable any DPPI channel connections.
  • Clear all bits in the INTEN register.
  • Configure the new peripheral. 

GPIO Pin Mapping

• Basic rule is that peripheral instances of a certain power domain can only be mapped to the GPIO port of this power domain e.g., SPIM00 or UARTE00 can only be mapped to GPIO P2 (see block diagram at https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/overview.html)
• Some peripherals allow for "cross power-domain usage" e.g., UARTE20/21 would usually go to P1 but can connect across power domains to dedicated pins on P2.
• It's mainly about following the rules in this section of the data sheet: https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/chapters/pin.html